1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device having a write per bit function in page mode.
2. Description of the Background Art
FIG. 22 is a block diagram showing a conventional semiconductor memory device having a write per bit function in page mode. Before describing the write per bit function in page mode, a construction and an operation of a semiconductor memory device in FIG. 22 will be described below.
This semiconductor memory device has the construction allowing input and output of 4-bit data in parallel. A memory array 1 includes four memory array blocks B0-B3. Each memory array block is disposed correspondingly to each bit of the data. Each of memory array blocks B0-B3 includes a plurality of memory cells disposed in plural rows and plural columns.
An RAS buffer 2 receives an external row address strobe signal /RAS and generates an internal signal /RASI. The internal signal /RASI has the same phase as the external row address strobe signal /RAS. A CAS buffer 3 receives an external column address strobe signal /CAS, and generates an internal signal /CASI. The internal signal /CASI has the same phase as the external column address strobe signal /CAS. A W-buffer 4 receives an external data write control signal /W, and generates an internal signal /WI. The internal signal /WI has the same phase as the external data write control signal (external write signal) /W.
A row address buffer 5 receives an external address signal Add and generates a row address signal in response to fall of the internal signal /RASI. A row decoder 6 decodes the row address signal, and selects one row in each of the memory array blocks B0-B3.
The data of one row read from the memory cells in the selected one row is amplified by a sense amplifier included in a sense amplifier and IO gate 7 and is held.
A column address buffer 8 receives the external address signal Add, and generates a column address signal in response to the internal signal /CASI. A column decoder 9 decodes the column address signal and selects one column in each of the memory array blocks B0-B3. Thereby, the data selected in each of the memory array blocks B0-B3 is transmitted through an IO gate included in the sense amplifier and IO gate 7 to corresponding one of input/output lines IO0-IO3.
In a write operation, the data externally applied to external data input terminals WIO0-WIO3 is sent through four input circuits 10 to the input/output lines IO0-IO3, respectively.
In a read operation, the data on the input/output lines IO0-IO3 is sent through four output circuits 11 to external data output terminals RIO0-RIO3, respectively. An output control circuit 12 controls the output circuits 11 in response to an external output enable signal /OE.
A timing generator 13 is responsive to the internal signals /RASI, /CASI and /WI to generate various timing signals. This semiconductor memory device is formed on a semiconductor chip CH.
Now, the write per bit function in page mode will be described below. In the page mode, the memory cells in the selected one row are sequentially selected by repetitively dropping the external column address strobe signal /CAS, while maintaining the state where one row in each memory array block is selected in response to the fall of the external row address strobe signal /RAS. This mode allows random access within a range of one row in the memory matrix at a higher speed than the normal mode and with lower power consumption. The write per bit function is a function inhibiting the write of an arbitrary bit of externally applied data.
The semiconductor memory device in FIG. 22 has the write per bit function in page mode. Now, a specific construction of the input circuit 10 in the semiconductor memory device in FIG. 22 will be described below, and further the write per bit function in page mode will be described.
FIG. 23 is a block diagram showing one of the input circuits 10. The input circuit 10 includes a mask data input buffer 101, a data input buffer 102 and an IO buffer 103.
The mask data input buffer 101 is responsive to the internal signals /RASI and /WI, and receives the data through an external data input terminal WIOi to generate mask data MDi. The mask data MDi forms mask information MSKi. Here, "i" represents an integer from 0 to 3.
The data input buffer 102 is responsive to the internal signals /CASI and /WI, and receives the data through the external data input terminal WIOi to generate write data DBi.
The IO buffer circuit 103 is responsive to the mask information /MSKi, and applies the write data DBi to the input/output line IOi or inhibit the input. The input/output line IOi includes two input/output lines IO and /IO receiving complementary data.
FIG. 24 is a circuit diagram showing a specific construction of a mask data input buffer circuit 101 shown in FIG. 23. The mask data input buffer circuit 101 includes inverters G1-G8, NOR gates G9 and G10, inverter circuits INV1 and INV2, and a latch circuit LT1.
When the internal signal /RASI and internal signal /WI go to "L", the output of inverter G1 goes to "L", and the output of NOR gate G10 is maintained at "H" for a predetermined time period. Thereby, the inverter circuit INV1 is activated, and the inverter circuit INV2 is maintained at an active state for the predetermined time period. Therefore, the data at external data input terminal WIOi is fetched through the inverter circuit INV1, inverter G8 and inverter circuit INV2 to the latch circuit LT1. The latch circuit LT1 latches the data and outputs the same as the mask information MDi.
FIG. 25 is a circuit diagram showing a specific construction of the data input buffer circuit 102 in FIG. 23. The data input buffer circuit 102 includes inverters G11-G18, NOR gates G19 and G20, inverter circuits INV3 and INV4, and a latch circuit LT2.
When the internal signals /CASI and /WI go to "L", the output of inverter G11 goes to "L", and the output of NOR gate G20 is maintained at "H" for a predetermined time period. Thereby, the inverter circuit INV3 is activated, and the inverter circuit INV4 is maintained at the active state for the predetermined time period. Therefore, the data at external data input terminal WIOi is fetched through the inverter circuit INV3, inverter G18 and inverter circuit INV4 to the latch circuit LT2. The latch circuit LT2 latches the data and outputs the same as the write data DBi
FIG. 26 is a circuit diagram showing a specific construction of the IO buffer circuit 103 shown in FIG. 23. The IO buffer circuit 103 includes inverters G21 and G22, NAND gates G23 and G24, NOR gates G25 and G26, P-channel MOS transistors P1 and P2, and N-channel MOS transistors N1 and N2.
If the mask information /MSKi is "L" (write inhibit state), the outputs of NAND gates G23 and G24 are "H", and the outputs of NOR gates G25 and G26 are "L". Thereby, the transistors P1, P2, N1 and N2 are turned off. Thus, the write data DBi is not transmitted to the input/output lines IO and /IO.
If the mask information /MSKi is "H" (write enable state), NAND gates G23 and G24 as well as NOR gates G25 and G26 operate as the inverters, respectively. Thus, the write data DBi is transmitted to the input/output line IO, and the inverted data of write data DBi is transmitted to the input/output line /IO.
Referring to a timing chart of FIG. 27, the write per bit operation in page mode of the conventional semiconductor memory device shown in FIGS. 22-26 will be described below.
In response to the fall of the external row address strobe signal /RAS, the external address signal Add is fetched as a row address signal X. Thereby, one row in each memory array block is selected. If the external data write control signal /W is "L" when the external row address strobe signal /RAS falls, the data at external data input terminals WIO0-WIO3 is fetched as mask information /MSK0-/MSK3.
In an example shown in FIG. 27, the mask information MSK0 and /MSK2 goes to "L" (write inhibit state), and the mask information /MSK1 and /MSK3 goes to "H" (write enable state). Thereby, the external data input terminals WIO0 and WIO2 are maintained at the write inhibit state, and the external data input terminals WIO1 and WIO3 are maintained at the write enable state.
While maintaining the external row address strobe signal /RAS at "L", the external column address strobe signal /CAS is repetitively fallen to "L". In response to the fall of the external column address strobe signal /CAS, the external address signals Add are sequentially fetched as column address signals Y1, Y2, Y3 and Y4. Thereby, in each memory array block, the memory arrays on one row selected by the row address signal X are sequentially selected by the column address signals Y1, Y2, Y3 and Y4, respectively. The column selecting operation, which is responsive to the fall of the external column address strobe signal /CAS, is called a CAS cycle.
In a CAS cycle T1, the writing of data D01 at external data input terminal WIO0 and the data D21 at external data input terminal WIO2 is inhibited, and the writing of data D11 at external data input terminal WIOl and data D31 at external data input terminal WIO3 is carried out. Similarly, in each of CAS cycles T2, T3 and T4, the writing of data at external data input terminals WIO0 and WIO2 is inhibited, and the writing of data at external data input terminals WIO1 and WIO3 is carried out.
As described above, according to the write per bit operation in page mode of the conventional semiconductor memory device shown in FIGS. 22-26, the mask information was fetched when the external row address strobe signal /RAS fell, and in every CAS cycle thereafter, the write inhibit state or write enable state of each external data input terminal is determined, depending on the fetched mask information. Thus, the mask information, which was fetched when the external row address strobe signal /RAS fell, affects every CAS cycle thereafter, so that the mask information in each cycle has no arbitrariness.